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Ternarylogic LLC
8 Harvey Court, Suite 707
Morristown, NJ 07960

973-722-8228
admin@ternarylogic.com
www.ternarylogic.com

 

Ternarylogic LLC Portfolio

Ternarylogic's portfolio currently comprises over 30 inventions which can be arranged in the following categories:
1. Basic building blocks and methods, including:
    n-valued switches, inverters and logic devices;
    novel n-valued arithmetical methods;
    methods for eliminating multipliers.
2. LFSR devices and methods, including:
    n-valued scramblers and descramblers;
    n-valued sequence generators;
    detectors of binary and n-valued sequences;
    synchronization methods;
    n-valued Gold sequence generators;
    Galois configuration self synchronizing scramblers and descramblers;
    memory based LFSR solutions;
3. Memory and storage devices and methods:
    logic based latches and memories;
    multi-valued storage on optical disks;
4. Fast FIR filters using n-valued arithmetic;
5. Improved correlation methods;
6. Encipherment devices and methods, including:
    orthogonal transposition methods;
    substitution coding to statistically uniform distributed ciphers;
7. Error-correcting coding and decoding methods, including:
    deterministic error correction of convolutional codes;
    fast Reed Solomon error correction;
    multi-valued LDPC coding and decoding;
    determining and using multi-valued parity symbols;

Several other inventions are currently under development.

Ternarylogic LLC Portfolio of Issued and Pending Patents
Status on January 17, 2008

 

USPTO Pub Number

Title

Status

1

20050053240

Ternary And Higher Multi-Value Digital Scramblers/Descramblers

Pending

2

7,002,490

Ternary And Higher Multi-Value Digital Scramblers/Descramblers

Issued

3

20050185796

Ternary And Multi-Value Digital Scramblers, Descramblers And Sequence Generators

Pending

4

20070110229

Ternary And Multi-Value Digital Scramblers, Descramblers And Sequence Generators

Pending

5

7,218,144

Single And Composite Binary And Multi-Valued Logic Functions From Gates And Inverters

Issued

6

7,355,444

Single And Composite Binary And Multi-Valued Logic Functions From Gates And Inverters

Issued

7

7,064,684

Sequence Detection By Multi-Valued Coding And Creation Of Multi-Code Sequences

Issued

8

7,277,030

Sequence Detection By Multi-Valued Coding And Creation Of Multi-Code Sequences

Issued

9

20050278661

Multi-Valued Digital Information Retaining Elements And Memory Devices

Allowed

10

20050184888

Generation And Detection Of Non-Binary Digital Sequences

Pending

11

20060031278

Multi-value Digital Calculating Circuits, Including Multipliers

Pending

12

20060164883

Multi-valued scrambling and descrambling of digital data on optical disks and other storage media

Pending

13

7,365,576

Binary digital latches not using only NAND or NOR circuits

Issued

14

20070005673

The Creation and Detection of Binary and Non-Binary Pseudo-Noise Sequences Not Using LFSR Circuits

Pending

15

20070071068

Encipherment Of Digital Sequences By Reversible Transposition Methods

Pending

16

20070088997

Generation And Self-Synchronizing Detection Of Sequences Using Addressable Memories

Pending

17

20070098160

Scrambling And Self-Synchronizing Descrambling Methods For Binary And Non-Binary Digital Signals Not Using LFSRs

Pending

18

20070226594

Error Correcting Decoding For Convolutional And Recursive Systematic Convolutional Encoded Sequences

Pending

19

20070258516

Multi-Valued Check Symbol Calculation In Error Detection And Correction

Pending

20

20070208796

Methods And Apparatus In Finite Field Polynomial Implementations

Pending

21

20070239812

Binary And n-Valued LFSR And LFCSR Based Scramblers, Descramblers, Sequence Generators And Detectors In Galois Configuration

Pending

22

PCT/US07/xxxxx

Binary And n-Valued LFSR And LFCSR Based Scramblers, Descramblers, Sequence Generators And Detectors In Galois Configuration

Pending

23

20080016431

Error Correction By Symbol Reconstruction In Binary And Multi-Valued Cyclic Codes

Pending

24

20080040650

Symbol Reconstruction In Reed-Solomon Codes

Pending

25

20080104479

Symbol Error Correction By Error Detection And Logic Based Symbol Reconstruction

Pending

26

xx/xxx,xxx

Multi Valued Digital Signal Scramblers, Descramblers and Sequence Detectors in Implementation with Functions Over GF(n)

Pending

27

20080016432

Error Correction In Multi-Valued (p,k) Codes

Pending

28

xx/xxx,xxx

Implementing Logic Functions with Non-Magnitude Based Physical Phenomena

Pending

29

xx/xxx,xxx

Encipherment for Modifying the Statistical Distribution of Symbols in a Message

Pending

30

xx/xxx,xxx

Multi-state, Multi-input Switching Functions and Multiplications

Pending

31

xx/xxx,xxx

Novel Binary and N-State Linear Feedback Shift Registers (LFSRs)

Pending

32

xx/xxx,xxx

N-State Ripple Adder Scheme Coding with Corresponding N-State Ripple Adder Scheme Decoding

Pending

33

xx/xxx,xxx

Multi-state Symbol Error Correction in Matrix Based Codes

Pending

34

xx/xxx,xxx

Multi-state Latches from n-state Inverters

Pending

Comments:

I. A Patent or Patent Application with a repeated title may be a continuation of a previous Patent or Patent Application.

II. A USPTO or PCT number xx/xxx,xxx indicates that USPTO has provided a filing date and a filing number for the application, but that the application has not been made public.  Accordingly details of the application will be treated as confidential by Ternarylogic LLC.

III. All of the above Patents and Pending Patents are assigned to Ternarylogic LLC.

IV. The issued and allowed Patents and current Office Actions with USPTO indicate that Ternarylogic LLC has introduced a number of pioneering concepts that have passed scrutiny by different USPTO Examiners.  This provides confidence that most if not all of our patent applications will likely lead to issued patents.