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Binary Logic



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Ternarylogic LLC


Binary Logic

Ternarylogic LLC offers a portfolio of inventions and technology that is based on MVL switching or n-state logic with n > 2.  In the course of creating the n-state solutions it was demonstrated that some of the inventions can be used in binary switching.

Following are some elements of Ternarylogicís IP portfolio specifically targeted towards binary applications.

1. Correlation amplification
Comparing sequences of binary symbols that are comparatively identical by correlation is difficult. It would be beneficial if the differences between the sequences could be enhanced or amplified.  This can be achieved by recoding binary symbols in a sequence and the sequence for comparison in a higher value set of symbols and correlating the recoded sequences.

2. Binary latches not using NANDs or NORs
Binary latches and related flip-flops generally apply NAND or NOR circuitry.  Very popular is also using inverters in feedback configuration.  Non-commutative binary logic functions can be used to create effective binary latches using a minimal number of inverters.

A patent on this invention has been issued as patent 7,365,576. The invention is based on a causal switching model that allows to model logic functions with feedback. It is shown that a combination of an AND and an OR function creates a memory latch. Two identical non-commutative functions, which represent the non-commutative expression a > b, allow for the creation of a very simple and inverterless binary latch.

3. Self-synchronizing LFSR descramblers in Galois configuration
LFSR based scramblers and descramblers in Galois configuration can be faster than the currently used Fibonacci configurations.  The rules for equivalence between the two configurations ensure compatibility.

A known disadvantage of the self-synchronizing LFSR scrambler and descrambler in Fibonacci configuration is that an LFSR with more than 2 taps require execution of additional XOR functions within a clock cycle. However, Fibonacci configured descramblers are preferred because of their self-synchronizing properties. Such a descrambler will flush errors and regain synchronization after the flushing of the shift register. To counter the disadvantage of multiple functions one generally applies LFSRs with just two taps, which are not always optimal.

Patent application 20070239812 discloses self-synchronizing scramblers and descramblers with LFSRs in Galois configuration. These LFSRs have more than 2 taps and functions and provide a greater variety of scrambling, while still being executed in one clock cycle and being self-synchronizing.

4. LFSR based pn-sequence detector
An LFSR based detector of pseudo-noise (pn) sequences generates all 0s or all 1s for the appropriate pn-sequence in Fibonacci configuration and a mix of 0s and 1s if a wrong sequence is entered.

Detection of binary sequences is commonly performed by correlation techniques. This means that a sequence is compared bit-by-bit with a known sequence. Usually this requires that one locally generates the sequence that needs to be detected.

A pseudo-noise sequence is often generated by a self-running LFSR. The pn-sequence is determined by the initial content of the shift register. The pn-generator is from one perspective not provided with an input. Patent application 20050184888 discloses how one can create an LFSR based descrambler for detection of an LFSR based generated pn-sequence. Detection of the pn-sequence generates a constant stream of 1s (or 0s if one so prefers).
5. LFSR based phase detection of pn-sequence
LFSR based detector in Galois configuration can distinguish between different orthogonal phases of a pn-sequence.

6. Orthogonal hopping rules
Reversible orthogonal hopping rules derived from a pseudo-noise sequence.

7. Convolutional error correcting decoding
Deterministic error correction of convolutional coded sequences is enabled. A trellis or maximum likelihood method is not used.  The method is simple, fast and easy to implement.

8.  Binary scrambling of n-state symbols
N-state symbols in QAM-N are often scrambled to improve peak-to-average power ratio of the signal. N-state scrambling in binary form in the logic stage is much easier and much more effective. And it can be done in a self-synchronizing mode.