Ternarylogic LLC

Advanced computing? No matter how complex a program or application, how large the memory or how fast the internal clock of a processor or digital circuit, in essence we are still dealing with a computer being a relatively simple switching machine. The buidling blocks of these switching machines are the simplest of simple switching devices: binary switches. This is curious, as virtually no process in the real world (including mathematics) is a binary process. Almost every concept we deal with has multiple possible states.

If you are one of those people who have an innate curiosity and wonder how things can be different, you have come to the right place. You probably have heard many times that current digital technology is binary. Why not ternary, you may wonder. Or why not a 256 state logic? What would non-binary logic mean? Find out here and on related web sites.

Ternarylogic LLC is an R&D company that develops Intellectual Property (IP) in multi-state switching technology and n-state arithmetic.

Our inventions are related to novel ways of using non-binary switching functions.

The Ternarylogic portfolio has over 50 inventions and covers:
- building blocks, such as switches and memories;
- self-synchronizing LFSR based descramblers in Galois and Fibonacci configuration;
- n-state symbol sequence generators;
- sequence detectors;
- correlation methods;
- error-correcting coding (BCH, convolutional and product codes);
- encryption, including Feistel network based codes and ECC coding;
- radix-n arithmetical methods; and
- Galois Field arithmetic.

Access to Our Portfolio and Licensing Opportunities

This web site comprises a wealth of information, links, white papers and references to patents and patent applications. Feel free to download any of the documents.  Please be aware that none of the patented inventions disclosed are in the public domain. No license is provided to use any part of our Intellectual Property.  But you can certainly review it. Or invent something new, if you are inspired by it.

A list of Issued Patents and Published Patent Applications is provided in a document that can be downloaded for www.ternarylogic.com/portfolio.pdf. This document has live links to at least some of the disclosures. Please, visit the US Patent Office web site here for an up-to-date listing of all issued patents.

Contact us if you wish to apply any of our inventions or obtain a license. While we encourage you to review all the disclosed matter, we frown upon any infringement of our IP rights. What does this mean? It means that you cannot use, make, sell, offer to sell, or import any of our inventions that are protected by US Patents in the USA without our express and written permission. Please review the Infringement Statute to update your knowledge about patent infringement in the USA.

Immediate Applications

Non-binary concepts are currently used in error-correcting decoding such as in Reed Solomon (RS) codes. The n-state logic functions are generally implemented as additions and multiplications over Finite or Galois Fields (GF(n)).

A brief overview of a finite field GF(4) is provided here, including an introduction to alternate finite fields. RS-FEC (forward-error-correcting) codes often apply to 256-state symbols. A 256-state symbol is then represented by a byte of 8-bits.

One Ternarylogic invention "combines" a multiplication with a constant over GF(n) with an addition over GF(n) into a single function represented by a single stored truth table. Such a single function in GF(256) only requires 64 kB in memory, is fast and circumvents the unwieldy multiplication and the XOR additions.

Another novel application is a non-binary error correcting convolutional code. Decoding of convolutional codes often is illustrated with a trellis diagram. It is easy to see that a trellis of a non-binary convolutional code (such as a 256-state convolutional code) becomes too complex to handle. A novel decoding approach, for which Ternarylogic LLC has obtained a patent, is extremely fast and enable decoding of n-state convolutional codes. See a description here. This very fast decoding approach of convolutional codes also applies to the binary version.

Another invention is related to rapid decoding of the ubiquitous Reed Solomon error correcting code. By determining comparative intermediate RS coding states, one can rapidly determine error locations and correct these errors. The intermediate coding states are evaluated as symbols are being received, thus circumventing the need to calculate roots of an error location polynomial only after all symbols have been received.

Help with the Concepts

The concepts of n-state switching and its relation with binary logic or switching may initially be somewhat confusing.

A web site which explains the basic concepts in n-state switching is provided here. Or go to www.nstatelogic.com.

If you want to see an example of a 3-valued switching function click here. A 3-valued ripple adder program can be viewed here. The application of n-state switching in LFSR based scramblers and descramblers can be viewed here, and provides an embedded program actually running scramblers and descramblers.